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Researchers from the University of Arkansas, Fayetteville, say they have made a significant step forward in learning how to produce polycrystalline silicon using a process that creates significantly larger grains at lower temperatures. The group thinks it may be a big step toward getting photovoltaic energy competitive with fossil fuel sources.

The Arkansas group, lead by Hameed Naseem, professor of electrical engineering and director of the university’s Solid State Lab, uses what they call a topdown aluminum-induced crystallization process to create poly-silicon with grains as wide as 150 µm at temperatures in the 100-300°C range

AIC has been used for several years to create small-grained poly-silicon, and early as 2001 Naseem, et al, published on how the method could be used to create 0.5 µm grains at 150°C.

In a typical AIC process, some form of chemical vapor deposition first is used to form an initial layer of amorphous silicon. Next, a layer of aluminum is deposited using vacuum deposition or some similar method. Finally, the silicon–aluminum layer is annealed, at which point the silicon and aluminum exchange places, and the aluminum catalytically assists the formation conversion of the amorphous silicon to poly-silicon during the exchange. Much of the layer-exchange system was pioneered by Oliver Nast and others at the University of New South Wales (Sydney) in the late 1990s and early 2000s.

Naseem tells me that what distinguishes his “topdown” AIC approach is that the aluminum simply diffuses through the silicon, causing the conversion to a p-type polycrystalline form rather than exchanging places. Naseem says that with TAIC, as the aluminum begins to diffuse, “the poly-silicon starts as nano crystalline material that coalesces almost explosively and produce these large grains.

He traced his group’s work back to problems NASA was identifying in semiconductors in the 1980s and 1990s. He says the semiconductors were failing and the problem turned out to be related to aluminum connects that would heat up and contaminate the silicon in the semiconductor. Further investigation showed that the amorphous silicon in the semiconductor was being damaged because it was being converted to poly-silicon. Although this was definitely a “problem” for NASA, other researchers, such as Naseem, realized that this ability could be put to positive use.

Naseem says there are several advantages to his group’s approach over other poly-silicon production techniques. Other techniques require require hours of heating at much higher temperatures and only produces grains in the 0.5-5 µm range. Furthermore, the processes necessitate batch processing.

Instead, TAIC rapidly provides large grains and lower temperatures, and, Naseem tells me, “It is perfectly suitable to making continuous film via automated and semi-automated processes. It can easily be annealed through belt annealing.”

Obviously, these researchers have the idea of making some large leaps in reducing the production cost of solar cells. “The problem with solar energy has been its cost per kilowatt hour. This applies to both production and consumption. With minimal further refinements, our technology will address this problem. The goal is to reduce the costs of silicon-based photovoltaics below those of traditional fossil-fuel-based methods such as coal, petroleum and natural gas,” Naseem says in a university press release.

Naseem says the next step for the group is to start testing small prototypes of photovoltaic cells and hopes to achieve a 12% module efficiency. To this end, it is working with a start-up company, Silicon Solar Solutions, to begin testing and, hopefully, establish a proof-of-concept continuous film processing demonstration. The company received an SBIR Phase 1 grant in late 2010.

ADDING: Naseem is actually a founder and the CTO of Silicon Solar Solutions. For more information about the company, readers might check out this story about it competing in the “Cleantech Open” business competition.

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A 5 nm silicon nanowire can be repeatedly broken and reconnected by applying a pulse of varying voltage through the silicon oxide, creating a two-terminal resistive switch. A chip with 1000 of these silicon-oxide/silicon nanowire memory elements has been assembled as a proof-of-concept.(Credit: Jun Yao/Rice.)

It’s not often that “plain vanilla” silicon oxide makes the front page of a paper like the New York Times, but it happened when Rice University scientists announced that they have created the first two-terminal memory chips based on silicon oxide in a way that they say should be easily adaptable to nanoelectronic manufacturing techniques, and promises to extend the limits of miniaturization subject to Moore’s Law.

Their technique creates nanocrystal wires that are as small as 5 nanometers wide, far smaller than circuitry in even the most advanced computers and electronic devices. The Rice group believes its nanocrystal conductors could lead to massive, robust 3-D storage.

“The beauty of it is its simplicity,” says James Tour, Rice’s T.T. and W.F. Chao chair in chemistry as well as a professor of mechanical engineering and materials science and of computer science. That, he said, will be key to the technology’s scalability. Silicon-oxide switches or memory locations require only two terminals, not three (as in flash memory), because the physical process doesn’t require the device to hold a charge.

According to the Rice press release:

“[Graduate student] Jun Yao sandwiched a layer of silicon oxide, an insulator, between semiconducting sheets of polycrystalline silicon that served as the top and bottom electrodes.

“Applying a charge to the electrodes created a conductive pathway by stripping oxygen atoms from the silicon oxide and forming a chain of nano-sized silicon crystals. Once formed, the chain can be repeatedly broken and reconnected by applying a pulse of varying voltage.”

Layers of silicon-oxide memory can be stacked in three-dimensional arrays. “I’ve been told by industry that if you’re not in the 3-D memory business in four years, you’re not going to be in the memory business. This is perfectly suited for that,” Tour says.

Silicon-oxide memories are compatible with conventional transistor manufacturing technology, says Tour, who recently attended a workshop by the National Science Foundation and IBM on breaking the barriers to Moore’s Law, which states the number of devices on a circuit doubles every 18 to 24 months.

Austin tech design company PrivaTran is already bench testing a silicon-oxide chip with 1,000 memory elements built in collaboration with the Tour lab.

The findings were published in Nano Letters.

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